1. Field of the Invention
This invention relates to a circuit and a method for protecting circuits from electrostatic discharge ESD. More particularly this invention relates to a circuit and a method which utilizes a dynamic floating circuit in conjunction with a silicon-controlled rectifier SCR in order to provide ESD protection for electronic circuits.
2. DESCRIPTION OF RELATED ART
Today, conventional electrostatic protection circuits utilize capacitors and silicon-controlled-rectifiers SCRs. FIGS. 1a and 1b show a lateral SCR (LSCR) ESD structure. This is the most basic SCR structure. In FIG. 1a, the SCR is imade up of P-N-P-N structure. The circuit model in fig. 1b shows the anode 110 attached to a PNP transitor 115 and a resistor 125. FIG. 1b further shows an NPN transistor 145 and another resistor 135 attached to the cathode of the SCR 140.
FIGS. 1c and 1d show a low-voltage trigger SCR (LVTSCR) ESD structure. This structure is described in U.S. Pat. No. 5,465,189. This structure is popular due to the low-voltage trigger. In FIG. 1c, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 1d shows the anode 150 attached to a PNP transitor 155 and a resistor 165. FIG. 1d further shows an NPN transistor 185 and another resistor 175 attached to the cathode of the SCR 180. In addition, an FET trigger device 195 is shown in FIG. 1d. 
FIGS. 2a and 2b show a floating-well SCR (FWSCR) ESD structure. This structure is exhibited in U.S. Pat. 5,945,714. In FIG. 2a, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 2b shows the anode 210 attached to a PNP transitor 215. FIG. 2b further shows an NPN transistor 245 and another resistor 235 attached to the cathode of the SCR 240.
FIGS. 2c and 2d show a MOS-incorporated-triggering SCR (MITSCR) ESD structure. This structure is exhibited in U.S. Pat. No. 5,986,307. In FIG. 2c, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 2d shows the anode 210 attached to a PNP transitor 215 and a resistor 225. FIG. 2d further shows an NPN transistor 245 and another resistor 235 attached to the cathode of the SCR 240.
U.S. Pat. No. 6,011,420 (Watt, et al.) xe2x80x9cESD Protection Apparatus Having Floating ESD Bus and Semiconductor Structurexe2x80x9d discloses an ESD protection scheme where a single ESD protection structure is connected to multiple pads. The circuit uses an FET-triggered SCR.
U.S. Pat. No. 5,959,821 (Voogel) xe2x80x9cTriple-Well Silicon Controlled Rectifier with Dynamic Holding Voltagexe2x80x9d describes a triple-well SCR with a circuit to control the voltage of the p-well. The triple-well structure is used for isolation from ground and to allow insertion of a control circuit for controlling the holding voltage of the SCR.
U.S. Pat. No. 5,400,202 (Metz, et al.) xe2x80x9cElectrostatic Discharge Protection Circuit for Integrated Circuitsxe2x80x9d discloses an FET-triggered SCR to provide ESD protection for circuits. A trigger circuit which is activated by an ESD event triggers SCR latch-up.
It is the objective of this invention to provide a circuit and a method to protect electronic circuits from electrostatic discharge ESD damage.
It is further an object of this invention to provide this ESD circuit protection by using a control circuit and a silicon-controlled rectifier SCR to dynamically isolate the electronic circuits during ESD events.
In addition, it is further the object of this invention to place the control circuit between the supply voltage and the SCR in order provide better immunity from permanent SCR latch-up during the return to normal operation after an electrostatic event.
The objects of this invention are achieved by a circuit which includes a floating-well circuit connected between the supply voltage Vdd and the N-well of a silicon-controlled rectifier, (SCR). In addition, the floating-well circuit contains a transistor switch which is turned on during normal operation effectively connecting the N-well of the SCR to the supply voltage (Vdd). Alternatively, the transistor switch is turned on to allow the SCR to provide isolation from ground and circuit protection during ESD events. This transistor control circuit also provides latch-up immunity by incorporating a discharge resistor which allows the SCR to revert back to its non-latched state after the occurrence of an electrostatic event.
The objects of this invention are achieved by a method of designing ESD protection circuits which provides for the connection of a floating-well circuit between the power supply voltage VCC and the N-well of an SCR. This method of protecting circuits from ESD damage also provides for the switching of a field effect transistor FET On during normal operation to effectively connect the N-well of the SCR to the supply voltage VCC. The circuit design method includes a capacitor attached from the supply voltage Vdd to the gate of the FET. During electrostatic events where the supply voltage contains spikes which momentarily increase the supply voltage beyond Vdd, the capacitor charges. The charging of this capacitor causes the FET switching transistor to turn Off. The switching Off of an FET during ESD events makes the SCR change into a FWSCR (floating-well SCR) to provide better ESD performance. However, in normal operation, the FET will be turned On so that the N-well will be reconnected to Vdd. Thus, the invention becomes a conventional SCR (Not FWSCR) to provide better latch-up immunity during normal operation. In addition, the method of designing ESD protection circuits provides latch-up immunity for the SCR by including a discharge resistor attached to the said capacitor. Once the ESD event has passed, the above capacitor discharges through the resistor during a pre-designed time constant. This allows the SCR to return to its non-latched state and allows the FET transistor to switch back On, effectively reconnecting the SCR to the supply voltage Vdd. Therefore, this method prevents the protection circuit from remaining in an SCR latched up state after the occurrence of an ESD event. This is what is known as latch-up immunity.